The present invention relates to a semiconductor device having an air gap between metal interconnects and a method for fabricating the same.
A conventional semiconductor device having an air gap between metal interconnects and a method for fabricating the same will now be described with reference to FIGS. 12A through 12D, 13A through 13C, 14A through 14C and 15A through 15C.
First, as shown in FIG. 12A, an insulating film 11 of an insulating material is formed on a semiconductor substrate 10 by known chemical vapor deposition (CVD) or spin coating, and then, connection plugs (not shown) are formed in the insulating film 11.
Next, as shown in FIG. 12B, a first barrier metal layer 12, a metal film 13 and a second barrier metal layer 14 are successively deposited on the insulating film 11, thereby forming an interconnect multi-layer film 15. The first barrier metal layer 12 and the second barrier metal layer 14 are formed by known sputtering, and the metal film 13 is formed by known sputtering, CVD or plating.
Then, as shown in FIG. 12C, a first interlayer insulating film 16 of an insulating material is formed on the interconnect multi-layer film 15 by the known CVD or spin coating, and a first resist pattern 17 is then formed on the first interlayer insulating film 16 by known lithography.
Subsequently, the first interlayer insulating film 16 is etched by using the first resist pattern 17 as a mask, thereby forming plug openings 18 in the first interlayer insulating film 16 as shown in FIG. 12D.
Next, as shown in FIG. 13A, a conducting film 19 is deposited on the first interlayer insulating film 16 by the sputtering, CVD or plating so as to fill the plug openings 18. In this case, when the plug opening 18 has an aspect ratio (a ratio of the thickness of the first interlayer insulating film to the diameter of the plug opening 18) larger than approximately 4, a void (space) 20 is formed in the conducting film 19 within the plug opening 18.
Then, as shown in FIG. 13B, a portion of the conducting film 19 present on the first interlayer insulating film 16 is removed by chemical mechanical polishing (CMP), thereby forming connection plugs 21 from the conducting film 19.
Thereafter, as shown in FIG. 13C, the first interlayer insulating film 16 is selectively dry etched, thereby reducing the thickness of the first interlayer insulating film 16. Thus, the connection plugs 21 protrude from the first interlayer insulating film 16.
Next, as shown in FIG. 14A, a second resist pattern 22 is formed on the first interlayer insulating film 16, and the first interlayer insulating film 16 is then etched by using the second resist pattern 22 as a mask, thereby forming a patterned first interlayer insulating film 16A as shown in FIG. 14B.
Then, the interconnect multi-layer film 15 composed of the first barrier metal layer 12, the metal film 13, the second barrier metal layer 14 is dry etched by using the second resist pattern 22, the patterned first interlayer insulating film 16A and the connection plugs 21 as a mask. Thus, lower metal interconnects 15A are formed from the interconnect multi-layer film 15 as shown in FIG. 14C.
The second resist pattern 22 is removed by ashing before or after the dry etching of the interconnect multi-layer film 15. In the case where the second resist pattern 22 is removed before the dry etching of the interconnect multi-layer film 15, an upper portion of each connection plug 21 is etched at the initial stage of the dry etching of the interconnect multi-layer film 15, and hence, an upper portion of each void 20 is opened so as to form an opening 20a as shown in FIG. 14C. Alternatively, in the case where the second resist pattern 22 is removed after the dry etching of the interconnect multi-layer film 15, the upper portion of each connection plug 21 is etched in the middle of the dry etching of the interconnect multi-layer film 15, and hence, the upper portion of each void 20 is opened so as to form the opening 20a as shown in FIG. 14C also in this case.
Next, the patterned first interlayer insulating film 16A and the insulating film 11 are etched. Thus, the thickness of the patterned first interlayer insulating film 16A is reduced and the thickness of a portion of the insulating film 11 not covered with the lower metal interconnects 15A is reduced as shown in FIG. 15A. During this etching, the upper portions of the connection plugs 21 are also etched, and hence, the openings 20a of the voids 20 are enlarged as shown in FIG. 15A.
Then, as shown in FIG. 15B, a second interlayer insulating film 23 is deposited over the semiconductor substrate by the CVD, thereby forming air gaps 24 in the second interlayer insulating film 23 between the lower metal interconnects 15A.
Subsequently, as shown in FIG. 15C, the second interlayer insulating film 23 is planarized by the CMP. Thus, a metal interconnect structure having the air gaps 24 is obtained.
Thereafter, a series of processes described above (from the procedure of FIG. 12B to the procedure of FIG. 15C) are repeatedly carried out, so that a multi-layer interconnect structure having an air gap can be obtained.
In the conventional method, when the aspect ratio of the plug openings 18 exceeds approximately 4, the voids 20 are formed within the connection plugs 21 as shown in FIG. 13A. Therefore, when the lower metal interconnects 15A having the air gaps 24 are formed, the complete openings 20a of the voids 20 are formed in the connection plugs 21 as shown in FIG. 15C.
Accordingly, the electric resistance between an upper metal interconnect formed on the second interlayer insulating film 23 and the connection plug 21 is largely increased, resulting in causing a problem that the characteristic of the device is degraded.
In this case, when the electric resistance between the upper metal interconnect and the connection plug 21 is larger beyond the limit, the reliability of the metal interconnect structure is largely lowered, and the semiconductor device cannot be operated in the worst case.
Furthermore, in the procedure for planarizing the second interlayer insulating film 23 by the CMP, an abrasive used in the CMP enters the voids 20, so as to cause a problem that the connection plugs 21 are corroded by the abrasive.
In consideration of the aforementioned conventional problems, an object of the invention is fabricating a high performance and highly reliable semiconductor device having an air gap between metal interconnects by preventing formation of a void in a connection plug during the fabrication thereof.
In order to achieve the object, the method for fabricating a semiconductor device of this invention comprises a first step of depositing a metal film on an insulating film on a semiconductor substrate; a second step of forming a first mask pattern on a first interlayer insulating film formed on the metal film and forming first plug openings in the first interlayer insulating film by etching the first interlayer insulating film with the first mask pattern used as a mask; a third step of forming first connection plugs by filling a first conducting film in the first plug openings; a fourth step of forming a second mask pattern on a second interlayer insulating film formed on the first interlayer insulating film and forming second plug openings respectively on the first connection plugs in the second interlayer insulating film by etching the second interlayer insulating film with the second mask pattern used as a mask; a fifth step of forming second connection plugs by filling a second conducting film in the second plug openings; a sixth step of forming the metal film into metal interconnects by etching the metal film with at least the first connection plugs and the second connection plugs used as a mask; and a seventh step of forming a third interlayer insulating film on the metal interconnects so as to form an air gap between the metal interconnects.
In the method for fabricating a semiconductor device of this invention, after forming the first plug openings in the first interlayer insulating film formed on the metal film, the first connection plugs are formed by filling the first conducting film in the first plug openings, and after forming the second plug openings respectively on the first connection plugs in the second interlayer insulating film formed on the first interlayer insulating film, the second connection plugs are formed by filling the second conducting film in the second plug openings. Therefore, the thickness of the first interlayer insulating film can be set to such a value that no void is formed in the first connection plugs, and the thickness of the second interlayer insulating film can be set to such a value that no void is formed in the second connection plugs. Accordingly, the semiconductor device having the air gap between the metal interconnects can be fabricated without forming voids in multi-layer connection plugs each composed of the first connection plug and the second connection plug.
The method for fabricating a semiconductor device preferably further comprises a step of forming multi-layer metal interconnects on the third interlayer insulating film by repeatedly carrying out procedures from the first step to the seventh step.
Thus, a semiconductor device with a multi-layer interconnect structure having air gap between metal interconnects can be fabricated without forming a void in connection plugs.
In the method for fabricating a semiconductor device, the first mask pattern preferably has an alignment accuracy measuring mark with a thickness not penetrated in etching for forming the first plug openings.
Thus, in an alignment mark region of the first interlayer insulating film, no recess is formed and hence the first conducting film is not filled, and therefore, a mistake in detecting a signal peak can be avoided in alignment accuracy measurement of the second mask pattern. As a result, the alignment can be highly accurately measured.
In the method for fabricating a semiconductor device, the second mask pattern preferably has an alignment accuracy measuring mark with a thickness not penetrated in etching for forming the second plug openings.
Thus, in an alignment mark region of the second interlayer insulating film, no recess is formed and hence the second conducting film is not filled, and therefore, a mistake in detecting a signal peak can be avoided in alignment accuracy measurement subsequently carried out. As a result, the alignment can be highly accurately measured.
The semiconductor device of this invention comprises metal interconnects formed on an insulating film on a semiconductor substrate; an interlayer insulating film formed on the metal interconnects; first connection plugs respectively connected to the metal interconnects and made from a first conducting film filled in first plug openings formed in the interlayer insulating film; second connection plugs respectively connected to upper faces of the first connection plugs and made from a second conducting film filled in second plug openings formed in the interlayer insulating film; and an air gap formed between the metal interconnects in the interlayer insulating film.
In the semiconductor device of this invention, the thickness of the first interlayer insulating film can be set to such a value that no void is formed in the first connection plugs and the thickness of the second interlayer insulating film can be set to such a value that no void is formed in the second connection plugs. Accordingly, a multi-layer connection plug composed of the first connection plug and the second connection plug can be prevented from having a void therein.